Decoding Formal Club Meeting - April 23, 2019
Date and time
Location
The Conference Center
2055 Gateway Place, San Jose, CA 95110 95110Description
Decoding Formal Club Meeting
Date: Tuesday, April 23, 2019
Time: 11:30am – 5pm
Location:
The Conference Center
2055 Gateway Place
San Jose, CA
Sponsored by: 
Attendance is complimentary, but space is limited, and pre-registration is required.
AGENDA:
11:30 - Registration and Lunch
1:00 - Presentations
Case Studies
Formal Verification of a Resource Allocator Unit
The Resource Allocator Unit (RAU) is responsible for allocating from a pool of many thousands of resources. This talk will describe how formal verification was used to prove that RAU correctly processed any combination and sequence of input requests to allocate, update or release resources.
Presented by: Vikas Minglani, Member of Technical Staff, Fungible Inc.
Formal Sign-off Meets Real-World Tapeout Schedules
How formal verification was used to accelerate the verification process and meet a challenging tapeout deadline for the Surface Write Unit (SWU) of a GPU.
Presented by: Jing Gao, Senior Engineer, Qualcomm
Special Topic
Logical Paradoxes, Mathematical Oddities, and Lessons for Formal Verification
Since the days of ancient Greece, people in general have been fascinated with the ideas of logical paradoxes: brain twisters like Zeno’s paradoxes of motion or Plutarch’s Ship of Theseus have filled thousands of pages of debate by philosophers and mathematicians over the centuries. Though a present-day FV geek might cynically wave off many of these with a few lines of Boolean algebra, there is a reason why we still find them fascinating to discuss. These paradoxes, and similar ideas and oddities discovered up through the modern era, reveal hidden complexities and issues in how we think, reason, and prove what we believe. Many of them still have lessons to teach us—lessons that are directly applicable to how we manage, execute, and evaluate Formal Verification tools and methodologies. In this talk, we will highlight a few of these mind-bending ideas, and talk about how recognizing what they teach us can lead to solidifying and improving the ways we do Formal Verification today.
Presented by: Erik Seligman, Author of Formal Verification: An Essential Toolkit for Modern VLSI Design and host of the Math Mutation podcast
4:00 - Networking Reception
What is Decoding Formal?
The Decoding Formal Club is a forum for formal enthusiasts, pioneers, leaders and colleagues who work to promote the sharing of ideas, advancement of formal technology, and adoption of formal sign-off within the industry. More information about past Decoding Formal Club meetings is here, including video presentations, photos and news. Look for updates on our blog.
Organized by
Oski believes that solving the hardest problem in semiconductor design is the best way to make our clients unstoppable. Functional verification is the hardest problem, and our clients trust us to verify their most challenging designs to ensure the highest quality possible.
Our comprehensive methodologies are changing the course of semiconductor verification. We deliver functional sign-off of mission critical blocks early in the development cycle, which helps our clients reduce costs and tape out with confidence.
The design world has pivoted from chip technology to parallelism to keep performance and power efficiency marching forward. It’s impossible for even the most advanced simulation methodologies to find the extreme corner-case bugs that have followed. Since it’s inception in 2005, Oski has been pioneering novel verification methodologies that are required to deliver high quality designs in this new world.